Verification Engineer

Note:- Must have 7+ years of industrial experience in Mixed signal Modelling.

We are seeking a detail-oriented mixed signal model engineer to verify behavioral models written in SystemVerilog, both logic and real number.
🔍 Responsibilities:
•           Extensive experience in modeling mixed signal circuits in SystemVerilog, including real number modeling
•           Strong understanding of HDL/SPICE co-simulations
•           Strong understanding of custom circuit schematic
•           Strong background in analog integrated circuit design
•           Proficiency in RTL design languages like SystemVerilog
•           Experience with formal equivalence checking tools like ESP

Must Have Skills:
HDL/SPICE 
SystemVerilog
Modeling mixed signal circuits