Silicon Design Verification Engineer

#Silicon hashtag#Design hashtag#Verification hashtag#Engineer 
Experience: Minimum 7 years
Visa: All visa
Location: Santa Clara, CA

Minimum Qualifications: 
Must be hands-on – hashtag#Verilog / hashtag#UVM coding
7+ years of hands-on experience in hashtag#Silicon / Design Verification
Strong System Verilog and hashtag#UVM coding skills
Experience with protocol verification and debug
Experience at hashtag#IP or subsystem level
Familiarity with processor-based verification environments
Experience with hashtag#VCS, hashtag#Xcelium / hashtag#Xsim, and waveform debug tools
Knowledge of C–System Verilog interaction and basic hashtag#C test writing
Scripting experience (hashtag#shell, hashtag#Makefile, hashtag#Perl)
Strong debugging and problem-solving skills