Lead Rtl Design Engineer

🔹 Key Responsibilities:
RTL design and micro-architecture development using SystemVerilog/Verilog
Perform Lint, CDC analysis, constraint development, and timing issue resolution
Collaborate closely with verification and physical design teams for seamless full-chip integration
Mentor junior engineers and drive RTL design best practices
🔹 Required Skills:
Strong hands-on experience in RTL coding
Expertise in Lint, CDC checks, timing reports, and SDC constraints