Digital Verification Engineer

🔍 Must-Have Skills
8+ years of experience in Digital Design Verification
Strong hands-on experience with SystemVerilog, UVM/OVM
Experience in Constrained Random Verification & Debugging
Scripting experience in Python or Perl
Experience with ASIC/SoC verification & Mixed Signal Co-simulation
💡 Nice to Have
Experience with SVA (SystemVerilog Assertions)
Coverage-driven verification & coverage modeling
Familiarity with AMBA protocols (AXI, AHB, APB)
Knowledge of serial protocols: SPI, I2C, I3C, UART, MDIO, JTAG
🎓 Qualifications
BS/MS in Electrical Engineering or related field