Design Verification Engineer

Hiring: Design Verification Engineer (DV) – Remote

We are looking for mid to senior DV Engineers to support advanced silicon verification (RISC-V based systems).

Key Skills:
RISC-V architecture & verification
SystemVerilog, UVM, SVA
Synopsys tools (VCS, VC Formal – DPV)
Python scripting, C/C++
AXI/CHI, cache-coherent systems

Nice to Have:
SoC integration, GLS, low power (CPF/UPF)
Vector/Matmul unit verification

Details:
Remote | 10+ months (extendable)
USC/GC only
LinkedIn + technical references required