Design Verification Engineer

Requirements
BSEE with 7+ years or MSEE with 5+ years of relevant experience.
Advanced knowledge of ASIC/FPGA verification flows, including simulation, testbench development, and post-silicon validation.
Strong expertise in SystemVerilog and Verilog.
Hands-on experience developing testbenches using UVM, OVM, or VMM methodologies.
Proficiency in C/C++ programming.
Scripting experience with Python or Perl.
Familiarity with industry-standard high-speed protocols (PCI Express, DDR, NAND Flash, etc.) is highly desirable.
Background in computer storage and networking is a plus.
Excellent communication skills, teamwork mindset, and the ability to take on diverse technical challenges.