Design Verification Engineer

🔧 Key Responsibilities
Develop verification environments, testbenches, and test cases from scratch
Drive IP-level verification from spec understanding to sign-off
Debug and resolve complex issues using industry-standard simulators
Work closely with cross-functional teams in a fast-paced environment
✅ Required Qualifications
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field
5–15 years of hands-on experience in Design Verification
Strong proficiency in SystemVerilog
Solid hands-on experience with UVM
Experience verifying one or more of the following IPs:
Interconnects (AXI, AHB, APB)
Memory Controllers
High-Speed Interfaces