Rtl Design Engineer

Role: RTL Design Engineer
Location: Santa Clara, CA Hybrid
Visa: USC, GC, H4EAD only
Duration: 6+ months
MOI: Skype 

Job Description: 
We are looking for an RTL Design Engineer to help design and verify high-performance hardware IPs.

Requirements
Experience with RTL design
Knowledge of SystemVerilog/Verilog
Familiarity with high-speed interfaces is a plus
Basic experience with Vivado/Vitis preferred