Infosysnow INC

Analog Design Engineer

Infosysnow INCContract
California
8 - 12 YearsFeb 26th, 2026
59 ViewsBe an Early Applicant
Required Skillset:
SerDes

Job Description

Analog Design Engineer - Any Visa
Location: Santa Clara, CA
Duration: 12 months

Minimum Qualifications
The ideal candidate should have a minimum of MS in Electrical Engineering with 8+ years of experience in high-speed serial links and deep knowledge of analog CMOS/BiCMOS designs in deep sub-micron process technologies.

Hands-on circuit design experience of SerDes blocks like Equalizers, PLL, Phase-Interpolators, CDR, etc. for 28Gbps+ data rates
Experience with design of inductors, transmission line, Trans-Impedance Amplifiers (TIA) and modulator drivers
Experience with the design of precision analog circuits like ADC/DACs
Experience with Mixed signal design/verification flows
Experience with full-chip designs, ESDs and verification flows

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