Advanced Fpga Verification Engineer

Hi,

I hope you are doing well.

We have an exciting Onsite opportunity for FPGA Verification Engineer based in Mountain View, CA. Please review the job details below and let me know if you are interested. If so, kindly share your updated resume

FPGA Verification Engineer 
 Location: Mountain View, CA (5 days onsite)

Job Summary

We are looking for a Senior FPGA Verification Engineer to independently execute and lead verification activities for complex FPGA/ASIC designs. The role requires strong expertise in SystemVerilog, UVM, and industry-standard EDA tools, with a focus on quality, automation, and on-time delivery.

Key Responsibilities

• Own and execute FPGA/ASIC verification tasks end-to-end
• Develop SystemVerilog/UVM verification environments
• Create test plans, functional & code coverage, and debug issues
• Collaborate with RTL, PD, DFT, and cross-functional teams
• Automate verification flows and reports using Python/Perl/TCL
• Ensure high-quality, zero-defect delivery
• Mentor team members and contribute to process improvements

Required Skills

• Strong experience in FPGA/ASIC verification
• SystemVerilog, UVM, Verilog, VHDL
• EDA tools: QuestaSim, Synopsys VCS (or similar)
• Coverage analysis, debugging, and verification methodologies
• Scripting: Python, Perl, TCL
• Excellent communication and teamwork skills

Education

• Bachelor’s or Master’s in Electrical / Computer Engineering or related field

Nice to Have

• Bus protocols: AXI, AHB, PCIe, SPI, I2C
• Exposure to physical design, STA, or DFT
• Advanced nodes (28nm and below)